This invention relates to automatic digital integrated circuit test systems and more particularly to a technique for generating signals to control the sequence of timing pulses and data to and from a device under test, and to decode error signals generated by incorrect device under test outputs.
2. Description of the Prior Art
For the testing of high speed digital integrated circuits, a typical automatic test system will contain a test vector memory that stores patterns that are to be applied to the input pins of the device under test ("DUT"), and data that is expected at the output pins of the DUT. DUT error data that is produced during a test may be stored in an error logging or compare memory. A typical automatic test system must be capable of testing devices having over 100 pins, with each pin requiring circuitry to control the application of timed data pulses to the DUT inputs, circuitry to generate strobe signals to control comparators connected to DUT outputs, and circuitry to decode error signals produced by the comparators in response to incorrect DUT outputs. The generation of the control signals and strobes must be accomplished with high timing accuracy in order to insure valid test results for high speed devices, even though these signals must travel over multiple signal paths with different propagation delays.
Under typical test conditions, it will be required to control the application of multiple timed data pulses to the DUT inputs in a single test clock cycle, and to generate multiple strobe signals. In addition, it is desirable to allow these signals to cross over the boundary of a test clock cycle and still have the error signal decoding circuitry be able to determine which test vector corresponds to which error signal. This must be done while maintaining full timing accuracy, and without introducing any increase in the comparator dead time.